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34com/60seg driver & controller for dot matrix lcd s6a0073 1 introduction s6a0073 is a dot matrix lcd driver & controller lsi which is fabricated by low power cmos technology. it can display 1, 2 or 4 lines with 5 8 or 6 8 dots format. functions character type dot matrix lcd driver & controller internal driver : 34 common and 60 segment signal output easy interface with 4 - bit or 8 - bit mpu clock synchronized serial interface 5 8 or 6 8 dots matrix possible extension driver interface possible bi - directional shift function all character reverse display display shift per line voltage converter for lcd drive voltage : 13 v max (2 times / 3 times) various instruction functions automatic power on reset features internal memory - character generator rom (cgrom) : 9,600 bits (24 0 characters 5 8 dot) - character generator ram (cgram) : 64 8 bits (8 characters 5 8 dot) - segment icon ram (segram) : 16 8 bits (96 icons max.) - display data ram (ddram) : 80 8 bits (80 characters max.) low power operation - power supply vo ltage range: 2.7 to 5.5v (v dd ) - lcd drive voltage range: 3.0 to 13.0v (v dd - v5) cmos process programmable duty cycle : 1/17, 1/33 (refer to table 1) inte rnal oscillator with an external resistor low power consumption tcp or bare chip available
s6a0073 34com/60seg driver & controller for dot matrix lcd 2 table 1. programmable duty cycles 1) 5 - dot font width display single - chip operation with exten sion driver line duty ratio displayable possible displayable possible icons numbers characters icons characters 1 1/17 1 line of 24 characters 60 1 line of 52 characters 80 2 1/33 2 lines of 24 characters 60 2 lines of 32 characters 80 4 1/33 4 lin es of 12 characters 60 4 lines of 20 characters 80 2) 6 - dot font width display single - chip operation with extension driver line duty ratio displayable possible icons displayable possible icons numbers characters characters 1 1/17 1 line of 20 char acters 60 1 line of 50 characters 96 2 1/33 2 lines of 20 characters 60 2 lines of 30 characters 96 4 1/33 4 lines of 10 characters 60 4 lines of 20 characters 96
34com/60seg driver & controller for dot matrix lcd s6a0073 3 block diagram power on reset (por) system interface serial 4-bit 8-bit instruction register (ir) instruction decoder address counter display data ram (ddram) 80 x 8-bit timing generator oscillator osc1 osc2 ie data register (dr) busy flag segment iconram (segram) 16 bytes character generator ram (cgram) 64 bytes character generator rom (cgrom) 9600 bits cursor & blink controller 60-bit shift register 60-bit latch circuit segment driver 34-bit shift register common driver com0- com33 seg1- seg60 parallel to serial converter and smooth scroll circuit lcd driver voltage selector v1 - v5 input/ output buffer voltage converter reset im rs/ cs e/ sclk rw/sid db4-db7 db3-db1 db0-sod vci c1 c2 v5out2 v5out3 vdd gnd(vss) 8 7 8 8 8 3 7 8 8 7 8 7 5/6 5 clk1 clk2 m ext d
s6a0073 34com/60seg driver & controller for dot matrix lcd 4 pad configuration seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 com9 com10 com11 com12 com13 com14 com15 com16 com25 com26 com27 com28 com29 com30 com31 com32 com33 vdd osc2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 2 1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 osc1 clk1 clk2 d m reset im ext ie vss1 rs/cs rw/sid e/sclk db0/sod db1 db2 db3 db4 db5 db6 db7 vci c2 c1 vss2 v5out2 v5out3 v5 v4 v3 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 com0 com1 com2 com3 com4 com5 com6 com7 com8 com17 com18 com19 com20 com21 com22 com23 com24 v1 v2 y x (0,0) chip size: 4870 x 5770 pad size: 100 x 100 unit: m m
34com/60seg driver & controller for dot matrix lcd s6a0073 5 pad center coordinat es pad pad coordinate pad pad coordinate pad pad coordinate num. name x y num. name x y num. name x y 1 seg44 - 1687 2719 44 ext - 986 - 2719 87 seg2 2269 497 2 seg45 - 1812 2719 45 ie - 861 - 2719 88 seg3 2269 622 3 seg46 - 2269 2122 46 vss1 - 736 - 2719 89 seg4 2269 747 4 seg47 - 2269 1997 47 rs / cs - 611 - 2719 90 seg5 2269 872 5 seg48 - 2269 1872 48 rw / sid - 486 - 2719 91 seg6 2269 997 6 seg49 - 2269 1747 49 e / sclk - 361 - 2719 92 seg7 2269 1122 7 seg50 - 2269 1622 50 db0/sod - 236 - 271 9 93 seg8 2269 1247 8 seg51 - 2269 1497 51 db1 - 111 - 2719 94 seg9 2269 1372 9 seg52 - 2269 1372 52 db2 14 - 2719 95 seg10 2269 1497 10 seg53 - 2269 1247 53 db3 139 - 2719 96 seg11 2269 1622 11 seg54 - 2269 1122 54 db4 264 - 2719 97 seg12 2269 1747 12 seg55 - 2269 997 55 db5 389 - 2719 98 seg13 2269 1872 13 seg56 - 2269 872 56 db6 514 - 2719 99 seg14 2269 1997 14 seg57 - 2269 747 57 db7 639 - 2719 100 seg15 2269 2122 15 seg58 - 2269 622 58 vci 764 - 2719 101 seg16 1813 2719 16 seg59 - 2269 497 59 c2 889 - 2719 102 s eg17 1688 2719 17 seg60 - 2269 372 60 c1 1014 - 2719 103 seg18 1563 2719 18 com9 - 2269 134 61 vss2 1139 - 2719 104 seg19 1438 2719 19 com10 - 2269 9 62 v5out2 1264 - 2719 105 seg20 1313 2719 20 com11 - 2269 - 116 63 v5our3 1389 - 2719 106 seg21 1188 2719 21 c om12 - 2269 - 241 64 v5 1514 - 2719 107 seg22 1063 2719 22 com13 - 2269 - 366 65 v4 1639 - 2719 108 seg23 938 2719 23 com14 - 2269 - 491 66 v3 1764 - 2719 109 seg24 813 2719 24 com15 - 2269 - 616 67 v2 2269 - 2116 110 seg25 688 2719 25 com16 - 2269 - 741 68 v1 2269 - 1991 111 seg26 563 2719 26 com25 - 2269 - 866 69 com24 2269 - 1866 112 seg27 438 2719 27 com26 - 2269 - 991 70 com23 2269 - 1741 113 seg28 313 2719 28 com27 - 2269 - 1116 71 com22 2269 - 1616 114 seg29 188 2719 29 com28 - 2269 - 1241 72 com21 2269 - 1491 115 seg3 0 63 2719 30 com29 - 2269 - 1366 73 com20 2269 - 1366 116 seg31 - 62 2719 31 com30 - 2269 - 1491 74 com19 2269 - 1241 117 seg32 - 187 2719 32 com31 - 2269 - 1616 75 com18 2269 - 1116 118 seg33 - 312 2719
s6a0073 34com/60seg driver & controller for dot matrix lcd 6 pad center coordinat es (continued) pad pad coordinate pad pad coordinate pad pad coordinate num. name x y num. name x y num. name x y 33 com32 - 2269 - 1741 76 com17 2269 - 991 119 seg34 - 437 2719 34 com33 - 2269 - 1866 77 com8 2269 - 866 120 seg35 - 562 2719 35 vdd - 2269 - 1991 78 com7 2269 - 741 121 seg36 - 687 2719 36 osc2 - 2269 - 2116 79 com6 2269 - 616 122 seg37 - 812 2719 37 osc1 - 1861 - 2719 80 com5 2269 - 491 123 seg38 - 937 2719 38 clk1 - 1736 - 2719 81 com4 2269 - 366 124 seg39 - 1062 2719 39 clk2 - 1611 - 2719 82 com3 2269 - 241 125 seg40 - 1187 2719 40 d - 1486 - 2719 83 com2 2269 - 116 126 seg41 - 1312 2719 41 m - 1361 - 2719 84 com1 2269 9 127 seg42 - 1437 2719 42 reset - 1236 - 2719 85 com0 2269 134 128 seg43 - 1562 2719 43 im - 1111 - 2719 86 seg1 2269 372
34com/60seg driver & controller for dot matrix lcd s6a0073 7 pin configuration of tcp tcp outline output side nc vdd osc2 osc1 clk1 clk2 d m reset im ext ie vss1 rs/cs e/sclk rw/sid db0/sod db1 db2 db3 db4 db5 db6 db7 vci c2 c1 vss2 v5out2 v5out3 v5 v4 v3 v2 v1 nc s6a0073
s6a0073 34com/60seg driver & controller for dot matrix lcd 8 nc vdd osc2 osc1 clk1 clk2 d m reset im ext ie vss1 rs/cs e/sclk rw/sid db0/sod db1 db2 db3 db4 db5 db6 db7 vci c2 c1 vss2 v5out2 v5out3 v5 v4 v3 v2 v1 nc 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 2 1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 nc nc com33 ... com9 seg60 ...... seg1 com0 ... com24 nc nc s6a0073 pad diagram 134-tcp-35mm
34com/60seg driver & controller for dot matrix lcd s6a0073 9 pin description pin (no) i/o name description interface vdd(35) for logical circuit (+3v, +5v) vss1, vss2 (46, 61) - power supply 0v (gnd) power supply v1 - v5 (68 - 64) bias voltage level for lcd driving vci (5 8) i input voltage to the voltage converter to generate lcd drive voltage (vci = 1.0 to 4.5v). seg1 - seg60 (86 - 128, 1 - 17) o segment output segment signal output for lcd drive. lcd com0 - com33 (85 - 69, 18 - 34) o common output common signal output for lcd drive lcd osc1, osc2 (37, 36) i(osc1), o(osc2) oscillator when using internal oscillator, connect external rf resistor. if external clock is used, connect it to osc1. external resistor/oscilla tor (osc1) clk1, clk2 (38, 39) o latch (clk1)/ shift ( clk2) clock when ext = "high", each outputs latch clock and shift clock for extension driver. extension driver c1, c2 (60, 59) i external capacitance input to use the voltage converter (2 times /3 times), these pins must be connected to the external capa citance. external capacitance m (41) o alternated signal for lcd driver output when ext = "high", outputs the alternating signal to convert lcd driver waveform to ac for extension driver. extension driver d(40) o display data interface when ext = "high", outputs extension driver data (the 61th dot's data) extension driver ext(44) i extension driver control signal when ext = "high", makes extension driver control signal enable, when ext = "low", suppress extra current consumption and clk1,clk2,m,d should be open. - reset (42) i reset pin initialized to low - ie (45) i selection pin of instruction set. when ie = "high", instruction set is selected as table 6. when ie = "low", instruction set is selected as table 10. -
s6a0073 34com/60seg driver & controller for dot matrix lcd 10 pin description (continued) pin (no) i/o name description interface v5out2 (62) o two times converter output the value of vci is converted two times. to use three times converter, the same capacitance as that of c1 - c2 should be connected here. v5 / capacitance v5out3 (63) three time s converter output the value of vci is converted three times. v5 im (43) i interface mode selection select interface mode with the mpu. when im = "low" : serial mode, when im = "high" : 4 - bit/8 - bit bus mode. - rs/cs (47) i register select /chip select when bus mode, used as register selection input. when rs/cs = "high", data register is selected. when rs/cs = "low", instruction register is selected. in serial mode, used as chip selection input. when rs/cs = "low", selected. when rs/cs = "high", not sel ected.(low access enable) mpu rw/sid (48) i read, write /serial input data in bus mode, used as read/write selection input. when rw/sid = "high", read operation when rw/sid = "low", write operation. in serial mode, used for data input pin. mpu e/sclk (4 9) i read, write enable /serial clock when bus mode, used as read, write enable signal. when serial mode, used as serial clock input pin. mpu db0/sod (50) i/o, o data bus 0 bit /serial output data in 8 - bit bus mode, used as lowest bidirectional data bit. during 4 - bit bus mode, open this pin. in serial mode, used as serial data output pin. if not in read operation, open this pin. mpu db1 - db3 (51 - 53) i/o data bus 1 - 7 in 8 - bit bus mode, used as low order bidirectional data bus. during 4 - bit bus mode or serial mode, open these pins. mpu db4 - db7 (54 - 57) in 8 - bit bus mode, used as high order bidirectional data bus. in case of 4 - bit bus mode, used as both high and low order. db7 used for busy flag output. during serial mode, open these pins. mpu
34com/60seg driver & controller for dot matrix lcd s6a0073 11 fu nction description system interface this chip has all three kinds of interface type with mpu : serial, 4 - bit bus and 8 - bit bus. serial and bus(4 - bit/8 - bit) are selected by im input, and 4 - bit bus and 8 - bit bus are selected by dl bit in the instruction regi ster. during read or write operation, two 8 - bit registers are used. one is data register (dr), the other is instruction register(ir). the data register(dr) is used as temporary data storage place for being written into or read from ddram/cgram/segram, targ et ram is selected by ram address setting instruction. each internal operation, reading from or writing into ram, is done automatically. hence, after mpu reads dr data, the data in the next ddram/cgram/segram address is transferred into dr automatically. a lso after mpu writes data to dr, the data in dr is transferred into ddram/cgram/segram automatically. the instruction register(ir) is used only to store instruction code transferred from mpu. mpu cannot use it to read instruction data. to select register, use rs/cs input pin in 4 - bit/8 - bit bus mode(im = "high") or rs bit in serial mode(im = "low"). table 2. various kinds of operations according to rs and r/w bits rs r/w operation l l instruction write operation (mpu writes instruction code into ir) l h re ad busy flag(db7) and address counter (db0 ? db6) h l data write operation (mpu writes data into dr) h h data read operation (mpu reads data from dr) busy flag (bf) when bf = "high", it indicates that the internal operation is being processed. so durin g this time the next instruction cannot be accepted. bf can be read, when rs = low and r/w = high (read instruction operation), through db7. before executing the next instruction, be sure that bf is not high. display data ram (ddram) ddram stores display d ata of maximum 80 8 bits (80 characters). ddram address is set in the address counter (ac) as a hexadecimal number. (refer to figure 1.) ac6 msb lsb ac5 ac4 ac3 ac2 ac1 ac0 figure 1. ddram address
s6a0073 34com/60seg driver & controller for dot matrix lcd 12 1) display of 5 - dot font width char acter (1) 5 - dot 1 - line display in case of 1 line display with 5 - dot font, the address range of ddram is 00h - 4fh (refer to figure 2). when ext = "high", extension driver will be used. figure 3 shows the example that 40 segment extension driver is added display position ddram address 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 seg1 s6a0073 seg60 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 17 18 19 20 21 22 23 24 seg1 s6a0073 seg60 08 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 10 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 18 17 11 12 13 14 15 16 17 18 19 20 21 22 23 24 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 18 19 20 21 22 23 24 (after shift left) (after shift right) 4f com9 com16 com9 com16 com9 com16 figure 2. 1 - line 24ch. display (5 - dot font width) extension driver (40seg) seg1 s6a0073 seg60 seg40 (after shift left) (after shift right) seg1 s6a0073 seg60 seg1 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 17 18 19 20 21 22 23 24 com9 com16 18 19 1a 1b 1c 1d 1e 1f 25 26 27 28 29 30 31 32 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 17 18 19 20 21 22 23 24 com9 com16 18 19 1a 1b 1c 1d 1e 1f 25 26 27 28 29 30 31 32 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 17 18 19 20 21 22 23 24 com9 com16 18 19 1a 1b 1c 1d 1e 25 26 27 28 29 30 31 32 20 4f figure 3. 1 - line 32ch. display with 40 seg. extension driver (5 - dot font width)
34com/60seg driver & controller for dot matrix lcd s6a0073 13 (2) 5 - do t 2 - line display in case of 2 line display with 5 - dot font, the address range of ddram is 00h - 27h,40h - 67h (refer to figure 4). when ext = "high", extension driver will be used. figure 5 shows the example that 40 segment extension driver is added. display position ddram address 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 17 18 19 20 21 22 23 24 seg1 s6a0073 seg60 s6a0073 seg1 seg60 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 com17 com24 (after shift left) (after shift right) com9 com16 com25 com32 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 17 18 19 20 21 22 23 24 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 com17 com24 18 58 com9 com16 com25 com32 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 18 19 20 21 22 23 24 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 com17 com24 27 67 com9 com16 com25 com32 figure 4. 2 - line 24ch. display (5 - dot font width) seg1 s6a0073 seg60 seg40 seg1 s6a0073 seg60 seg1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (after shift left) (after shift right) 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 17 18 19 20 21 22 23 24 com9 com16 18 19 1a 1b 1c 1d 1e 1f 25 26 27 28 29 30 31 32 20 00 com1 com8 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 com9 com16 18 19 1a 1b 1c 1d 1e 1f 40 com17 com24 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 com25 com32 58 59 5a 5b 5c 5d 5e 5f extension driver (40seg) 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 17 18 19 20 21 22 23 24 com9 com16 18 19 1a 1b 1c 1d 1e 25 26 27 28 29 30 31 32 4f com17 com24 com25 com32 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f 60 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e com17 com24 com25 com32 67 40 figure 5. 2 - line 32ch. display with 40 seg. extension driver (5 - dot font width)
s6a0073 34com/60seg driver & controller for dot matrix lcd 14 (3) 5 - dot 4 - l ine display in case of 4 line display with 5 - dot font, the address range of ddarm is 00h - 13h, 20h - 33h, 40h - 53h, 60h - 73h (refer to figure 6). when ext = "high", extension driver will be used. figure 7 shows the example that 40 segment extension driv er is added. display position ddram address (after shift left) (after shift right) 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 10 11 12 20 21 22 23 24 25 26 27 28 29 2a 2b 40 41 42 43 44 45 46 47 48 49 4a 4b 60 61 62 63 64 65 66 67 68 69 6a 6b seg60 s6a0073 seg1 com9 com16 com17 com24 com25 com32 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 10 11 12 21 22 23 24 25 26 27 28 29 2a 2b 41 42 43 44 45 46 47 48 49 4a 4b 61 62 63 64 65 66 67 68 69 6a 6b com9 com16 com17 com24 com25 com32 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 10 11 12 20 21 22 23 24 25 26 27 28 29 2a 40 41 42 43 44 45 46 47 48 49 4a 60 61 62 63 64 65 66 67 68 69 6a com9 com16 com17 com24 com25 com32 0c 2c 4c 6c 13 33 53 73 figure 6. 4 - line 12ch. display (5 - dot font width)
34com/60seg driver & controller for dot matrix lcd s6a0073 15 display position ddram address (after shift left) (after shift right) 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 10 11 12 20 21 22 23 24 25 26 27 28 29 2a 2b 40 41 42 43 44 45 46 47 48 49 4a 4b 60 61 62 63 64 65 66 67 68 69 6a 6b seg60 s6a0073 seg1 com9 com16 com17 com24 com25 com32 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 10 11 12 21 22 23 24 25 26 27 28 29 2a 2b 41 42 43 44 45 46 47 48 49 4a 4b 61 62 63 64 65 66 67 68 69 6a 6b com9 com16 com17 com24 com25 com32 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 10 11 12 20 21 22 23 24 25 26 27 28 29 2a 40 41 42 43 44 45 46 47 48 49 4a 60 61 62 63 64 65 66 67 68 69 6a com9 com16 com17 com24 com25 com32 0c 2c 4c 6c 13 33 53 73 0c 13 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 20 2c 2d 2e 2f 30 31 32 33 4c 4d 4e 4f 50 51 52 53 6c 6d 6e 6f 70 71 72 73 seg40 seg1 extension driver (40seg) 00 13 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 20 20 2d 2e 2f 30 31 32 33 40 4d 4e 4f 50 51 52 53 60 6d 6e 6f 70 71 72 73 0c 13 0d 0e 0f 10 11 12 0b 14 15 16 17 18 19 20 2c 2d 2e 2f 30 31 32 2b 4c 4d 4e 4f 50 51 52 4b 6c 6d 6e 6f 70 71 72 6b figure 7. 4 - line 20ch. display with 40 seg. extension driver (5 - dot f ont width)
s6a0073 34com/60seg driver & controller for dot matrix lcd 16 2) display of 6 - dot font width character (1) 6 - dot 1 - line display in case of 1 line display with 6 - dot font, the address range of ddram is 00h - 4fh (refer to figure 8). when ext = "high", extension driver will be used. figure 9 shows th e example that 40 segment extension driver is added. display position ddram address (after shift left) (after shift right) 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 10 11 12 seg60 s6a0073 seg1 com1 com8 com1 com8 0c 13 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 20 seg60 seg1 s6a0073 com9 com16 com9 com16 com9 com16 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 14 4f figure 8. 1 - line 20ch. display (6 - dot font width) extension driver (40seg) 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 17 18 19 20 21 22 23 24 seg1 s6a0073 seg60 s6a0073 seg1 seg36 (after shift right) com9 com16 18 19 25 26 seg1 seg60 1 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 17 18 19 20 21 22 23 24 18 19 25 26 00 1 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 17 18 19 20 21 22 23 24 18 25 26 (after shift left) com1 com8 com1 com8 com9 com16 com9 com16 1a 4f figure 9. 1 - line 26ch. display with 40 seg. extension driver (6 - dot font width)
34com/60seg driver & controller for dot matrix lcd s6a0073 17 (2) 6 - dot 2 - line display in case of 2 line display with 6 - dot font, the address range of ddram is 00h - 27h, 40h - 67h. (refer to figure 10) when ext = "high", extension driver will be used. figure 11 show s the example that 40 segment extension driver is added. display position ddram address (after shift left) (after shift right) com1 com8 seg60 s6a0073 seg1 seg60 seg1 s6a0073 com9 com16 com17 com24 com25 com32 00 1 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 10 11 12 0c 13 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 20 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 1 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 10 11 12 0c 13 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 20 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 00 1 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 10 11 12 0c 13 0d 0e 0f 10 11 12 14 15 16 17 18 19 20 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 com1 com8 com17 com24 com1 com8 com17 com24 com9 com16 com25 com32 com9 com16 com25 com32 14 54 27 67 figure 10. 2 - line 20ch. display (6 - dot font width) extension driver (40seg) com1 com8 seg1 s6a0073 seg60 s6a0073 seg1 seg36 (after shift right) com9 com16 seg1 seg60 (after shift left) com17 com24 com25 com32 00 1 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 17 18 19 20 21 22 23 24 18 19 25 26 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 1 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 17 18 19 20 21 22 23 24 18 19 25 26 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 00 1 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 17 18 19 20 21 22 23 24 18 25 26 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 com1 com8 com17 com24 com1 com8 com17 com24 com9 com16 com25 com32 com9 com16 com25 com32 1a 5a 27 67 figure 11. 2 - line 26ch. displa y with 40 seg. extension driver (6 - dot font width)
s6a0073 34com/60seg driver & controller for dot matrix lcd 18 (3) 6 - dot 4 - line display in case of 4 line display with 6 - dot font, the address range of ddarm is 00h - 13h, 20h - 33h, 40h - 53h, 60h - 73h (refer to figure 12). when ext = "high", extension driver will be used . figure 13 shows the example that 40 segment extension driver is added. display position ddram address (after shift left) (after shift right) 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 10 20 21 22 23 24 25 26 27 28 29 40 41 42 43 44 45 46 47 48 49 60 61 62 63 64 65 66 67 68 69 seg60 s6a0073 seg1 com9 com16 com17 com24 com25 com32 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 10 21 22 23 24 25 26 27 28 29 2a 41 42 43 44 45 46 47 48 49 4a 61 62 63 64 65 66 67 68 69 6a com9 com16 com17 com24 com25 com32 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 10 20 21 22 23 24 25 26 27 28 40 41 42 43 44 45 46 47 48 60 61 62 63 64 65 66 67 68 com9 com16 com17 com24 com25 com32 13 33 53 73 figure 12. 4 - line 10 ch. display (6 - dot font width)
34com/60seg driver & controller for dot matrix lcd s6a0073 19 display position ddram address (after shift left) (after shift right) 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 10 11 12 20 21 22 23 24 25 26 27 28 29 2a 2b 40 41 42 43 44 45 46 47 48 49 4a 4b 60 61 62 63 64 65 66 67 68 69 6a 6b seg60 s6a0073 seg1 com9 com16 com17 com24 com25 com32 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 10 21 22 23 24 25 26 27 28 29 2a 41 42 43 44 45 46 47 48 49 4a 61 62 63 64 65 66 67 68 69 6a com16 com17 com24 com25 com32 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 10 20 21 22 23 24 25 26 27 28 40 41 42 43 44 45 46 47 48 60 61 62 63 64 65 66 67 68 com9 com16 com17 com24 com25 com32 13 33 53 73 0c 0d 0e 0f 13 14 15 16 2c 2d 2e 2f 4c 4d 4e 4f 6c 6d 6e 6f seg1 seg36 extension driver (40seg) 0b 11 12 2b 4b 6b 0c 0d 0e 0f 13 14 15 16 2c 2d 2e 2f 4c 4d 4e 4f 6c 6d 6e 6f 10 30 50 70 0a 0b 11 12 2a 2b 4a 4b 6a 6b 0c 0d 0e 13 14 15 16 2c 2d 2e 4c 4d 4e 6c 6d 6e 09 29 49 69 figure 13. 4 - line 16ch. display with 40 seg. driver (6 - dot font width)
s6a0073 34com/60seg driver & controller for dot matrix lcd 20 timing generation circuit timing generation circuit generates clock signals for the internal operations. address counter (ac) address counter(ac) stores ddram/cgram/segram address, t ransferred from ir. after writing into (reading from) ddram/cgram/segram, ac is automatically increased (decreased) by 1. when rs = "low" and r/w = "high", ac can be read through db0 - db6 ports. cursor/blink control circuit it controls cursor/blink on/off a nd black/white inversion at cursor position. lcd driver circuit lcd driver circuit has 34 common and 60 segment signals for lcd driving. data from segram/cgram/cgrom is transferred to 60 - bit segment latch serially, which is then stored to a 60 - bit shift la tch. when each com is selected by 34 - bit common register, segment data also output through segment driver from 100 - bit segment latch. in case of 1 - line display mode, com0 - com17 have a 1/17 duty ratio, and in 2 - line or 4 - line mode, com0 - com33 have a 1/33 duty ratio.
34com/60seg driver & controller for dot matrix lcd s6a0073 21 cgrom (character generator rom) cgrom has 5 8 - dot 240 character pattern. cgram (character generator ram) cgram has up to 5 8 - dot 8 characters. by writing font data to cgram, user defined character can be used (refer to table 4). table 4. relationship between character code (ddram) and character pattern (cgram) 1) 5 8 dots character pattern 0 1 1 0 0 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 a5 a4 a3 a2 a1 a0 p7 p6 p5 p4 p3 p2 p1 p0 character code (ddram data) cgram address cgram data pattern number 0 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 . . . . . . . 0 0 0 x 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 b1 b0 x 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pattern 1 b1 b0 x 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . pattern 8 . . . . . . . . . . . . . . . . . . . . . . . .
s6a0073 34com/60seg driver & controller for dot matrix lcd 22 2) 6 8 dots character pattern 0 1 1 0 0 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 a5 a4 a3 a2 a1 a0 p7 p6 p5 p4 p3 p2 p1 p0 character code (ddram data) cgram address cgram data pattern number 0 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 . . . . . . . 0 0 0 x 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 b1 b0 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pattern 1 b1 b0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . pattern 8 . . . . . . . . . . . . . . . . . . . . . . . . 0 0 0 0 0 0 0 0 0 0 0 0 0 0 notes: 1. when be(blink enable bit) = "high", blink is controlled by b1 and b0 bit. in case of 5 - dot font width, when b1 = "1", enabled dots of p0 - p4 will blink, and w hen b1 = "0" and b0 = "1", enabled dots in p4 will blink, when b1 = "0" and b0 = ?0", blink will not happen. in case of 6 - dot font width, when b1 = "1", enabled dots of p0 - p5 will blink, and when b1 = "0" and b0 = "1", enabled dots of p5 will b link, when b1 = "0" and b0 = "0", blink will not happen. 2. "x" : don't care
34com/60seg driver & controller for dot matrix lcd s6a0073 23 segram (segment icon ram) segram has segment control data and segment pattern data. during 1 - line display mode, com0(com17) makes the data of segram enable to display i cons. when used in 2/4 - line display mode com0(com33) does that. its higher 2 - bits are blinking control data, and lower 6 - bits are pattern data (refer to table 5 and figure 8). table 5. relationship between segram address and display pattern segram address segram data display pattern 5 - dot font width 6 - dot font width a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 b1 b0 x s1 s2 s3 s4 s5 b1 b0 s1 s2 s3 s4 s5 s6 0 0 0 1 b1 b0 x s6 s7 s8 s9 s10 b1 b0 s7 s8 s9 s10 s11 s12 0 0 1 0 b1 b0 x s11 s12 s13 s14 s15 b1 b0 s13 s14 s15 s16 s17 s18 0 0 1 1 b1 b0 x s16 s17 s18 s19 s20 b1 b0 s19 s20 s21 s22 s23 s24 0 1 0 0 b1 b0 x s21 s22 s23 s24 s25 b1 b0 s25 s26 s27 s28 s29 s30 0 1 0 1 b1 b0 x s26 s27 s28 s29 s30 b1 b0 s31 s32 s33 s34 s35 s36 0 1 1 0 b1 b0 x s31 s32 s33 s34 s35 b1 b0 s37 s38 s39 s40 s41 s42 0 1 1 1 b1 b0 x s36 s37 s38 s39 s40 b1 b0 s43 s44 s45 s46 s47 s48 1 0 0 0 b1 b0 x s41 s42 s43 s44 s45 b1 b0 s49 s50 s51 s52 s53 s54 1 0 0 1 b1 b0 x s46 s47 s48 s49 s50 b1 b0 s55 s56 s57 s58 s59 s60 1 0 1 0 b1 b0 x s51 s52 s53 s54 s55 b1 b0 s61 s62 s63 s64 s65 s66 1 0 1 1 b1 b0 x s56 s57 s58 s59 s60 b1 b0 s67 s68 s69 s70 s71 s72 1 1 0 0 b1 b0 x s61 s62 s63 s64 s65 b1 b0 s73 s74 s75 s76 s77 s78 1 1 0 1 b1 b0 x s66 s67 s68 s69 s70 b1 b0 s79 s80 s81 s82 s83 s84 1 1 1 0 b1 b0 x s71 s72 s73 s74 s75 b1 b0 s85 s86 s87 s88 s89 s90 1 1 1 1 b1 b0 x s76 s77 s78 s79 s80 b1 b0 s91 s92 s93 s94 s95 s96 notes: 1. b1, b0 : blinking control bit control bit blinking port be b1 b0 5 - dot font width 6 - do t font width 0 x x no blink no blink 1 0 0 no blink no blink 1 0 1 d4 d5 1 1 x d4 - d0 d5 - d0 2. s1 - s80 : icon pattern on/off in 5 - dot font width s1 - s96 : icon pattern on/off in 6 - dot font width 3. "x" : don't care
s6a0073 34com/60seg driver & controller for dot matrix lcd 24 s61 s62 s63 s64 s65 seg61 seg62 seg63 seg64 seg65 5-dot font width (fw = 0) seg1 seg2 seg3 seg4 seg5 seg7 seg8 seg9 seg10 seg11 seg57 seg58 seg59 seg60 seg62 seg63 seg64 seg65 6-dot font width (fw = 1) seg6 seg12 seg61 seg66 seg55 seg56 s1 s2 s3 s4 s5 seg1 seg2 seg3 seg4 seg5 s6 s7 s8 s9 s10 seg6 seg7 seg8 seg9 seg10 s56 s57 s58 s59 s60 seg56 seg57 seg58 seg59 seg60 . . . s11 s12 s13 s14 s15 seg11 seg12 seg13 seg14 seg15 seg13 seg14 seg15 seg16 seg17 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s14 s15 s16 s17 s18 s13 s66 s65 s64 s63 s62 s61 s55 s56 s57 s58 s59 s60 seg18 . . . extension driver extension driver figure 14. relationship between segram and segment display
34com/60seg driver & controller for dot matrix lcd s6a0073 25 instruction descript ion outline to overcome the speed difference between internal clock of s6a0073 and mpu clock, s6a0073 performs internal operation by storing control information to ir or dr. the internal operation is determined according to the signal from mpu, composed of read/write and data bus. instruction can be divided largely four kinds, (1) s6a0073 function set instructions ( set display methods, set data length, etc.) (2) address set i nstructions to internal ram (3) data transfer instructions with internal ram (4) others . the address of internal ram is automatically increased or decreased by 1. when ie = "high", s6a0073 is operated according to instruction set 1 (table 6) and when ie = "low", s6a0073 is operated according to instruction set 2 (table 10). note: during internal operation, busy flag (db7) is read high. busy flag check must be preceded the next instruction. when an mpu program with busy flag (db7) checking is made, 1/2 f osc is necessary for executing the next instruction by the falling edge of the 'e' signal after the busy flag (db7) goes to "low".
s6a0073 34com/60seg driver & controller for dot matrix lcd 26 (1) instruction desc ription 1 (ie = "hig h") table 6. instruction set 1 instruction instruction code description executio n time re rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 (fosc= 2 70khz) clear display x 0 0 0 0 0 0 0 0 0 1 write "20" to ddram, and set ddram address to "00h" from ac. 1.53ms return home 0 0 0 0 0 0 0 0 0 1 x set ddram address to "00h" from ac and return cur sor to its original position if shifted. the contents of ddram are not changed. 1.53ms power down mode 1 0 0 0 0 0 0 0 0 1 pd set power down mode bit. (pd = "1" : power down mode set, pd = "0" : power down mode disable) 39 m s entry mode set 0 0 0 0 0 0 0 0 1 i/d s assign cursor moving direction, (i/d = "1": increment, i/d = "0": decrement, and display shift enable bit. (s = "1": make display shift of the enabled lines by the ds4 - ds1 bits in the shift enable instruction s = " 0": display shift disable) 39 m s 1 0 0 0 0 0 0 0 1 1 b/d segment bidirectional function. (bid = "1": seg60 ? seg1 bid = "0": seg1 ? seg60) display on/off control 0 0 0 0 0 0 0 1 d c b set display/cursor/blink on/off d = "1" : display on, d = "0" : display off, c = "1" : cursor on, c = "0" : cursor off, b = "1" : blink on, b = "0" : blink off. 39 m s extended function set 1 0 0 0 0 0 0 1 fw b/w nw assign font width, black/white inverting of cursor, and 4 - line display mode control bit. fw = "1" : 6 - dot font width, fw = "0" : 5 - dot font width, b/w = "1" : black/white inverting of cursor enable, b/w = "0" : black/white inverting of cursor di sable. nw = "1" : 4 - line display mode, nw = "0" : 1 - line or 2 - line display mode. 39 m s
34com/60seg driver & controller for dot matrix lcd s6a0073 27 table 6. instruction set 1 continued instruction instruction code description execution time re rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 (fosc= 2 70khz) cursor or display shift 0 0 0 0 0 0 1 s/c r/l x x cursor or display shift. s/c = "1" : display shift, s/c = "0" : cursor shift, r/l = "1" : shift to right, r/l = "0" : shift to left. 39 m s shift enable 1 0 0 0 0 0 1 ds4 ds3 ds2 ds1 (when dh = "1") determine the line for display shift . ds1 = "1/0": 1st line display shift enable/disable ds2 = "1/0": 2nd line display shift enable/disable ds3 = "1/0": 3rd line display shift enable/disable ds4 = "1/0": 4th line display shift enable/disable. 39 m s scroll enable 1 0 0 0 0 0 1 hs4 hs3 hs2 sh1 (when dh = "0") determine the line for horizontal smooth scroll. hs1 = "1/0" : 1st line dot scro ll enable/disable hs2 = "1/0" : 2nd line dot scroll enable/disable hs3 = "1/0" : 3rd line dot scroll enable/disable hs4 = "1/0" : 4th line dot scroll enable/disable. 39 m s function set 0 0 0 0 0 1 dl n re (0) dh re v set i nterface data length (dl = "1" : 8 - bit, dl = "0" : 4 - bit), numbers of display line when nw = "0", (n = "1" : 2 - line, n = "0" : 1 - line), extension register, re("0"), shift/scroll enable dh = "1" : display shift enable dh = "0" : dot scroll enable. and reverse bit rev = "1" : reverse display, rev = "0" : normal display. 39 m s 1 0 0 0 0 1 dl n re (1) be lp set dl, n, re("1") and cgram/segram blink enable (be) be = " 1/0" : cgram/segram blink enable/disable lp = "1" : l ow power mode lp = "0" : normal operation mode 39 m s
s6a0073 34com/60seg driver & controller for dot matrix lcd 28 table 6. instruction set 1 continued instruction instruction code description execution time re rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 (fosc=270khz) set cgram addr ess 0 0 0 0 1 ac5 ac4 ac3 ac2 ac1 ac0 set cgram address in address counter. 39 m s set segram address 1 0 0 0 1 x x ac3 ac2 ac1 ac0 set segram address in address counter. 39 m s set ddram address 0 0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 set ddram address in address counter. 39 m s set scroll quantity 1 0 0 1 x sq 5 sq 4 sq 3 sq 2 sq 1 sq 0 set the quantity of horizontal dot scroll. 39 m s read busy flag and address x 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 can be known whether during internal operation or not by reading bf. the contents of address counter can also be read. bf = ? 1 ? : busy state, bf = ? 0 ? : ready state. 0 m s w rite data x 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write data into internal ram (ddram / cgram / segram). 43 m s read data x 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read data from internal ram (ddram / cgram / segram). 43 m s note: when an mpu program with busy flag (db7) checking is mode, 1/2 f osc is necessary for executing the next instruction by the falling edge of the "e" signal after the busy flag (db7) goes to "low". "x": don't care
34com/60seg driver & controller for dot matrix lcd s6a0073 29 1) display clear rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 1 clear all the display data by writing "20h" (space code) to all ddram address, and set ddram address to "00h" into ac (address counter). return cursor to the original status, bring the cursor to the l eft edge on first line of the display. make entry mode increment (i/d = "1"). 2) return home: (re = 0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 1 x return home is cursor return home instruction. set ddram address to "00h" into the address c ounter. return cursor to its original site and return display to its original status, if shifted. contents of ddram does not change. 3) power down mode set: (re = 1) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 1 pd power down mode enable bit set instruction. when pd = "high", it makes s6a0073 suppress current consumption except the current needed for data storage by executing next three functions. make the output value of all the com/seg ports vdd make the com/seg output value of extension driver vdd by setting d output to "high" and m output to "low" disable voltage converter to remove the current through the divide resistor of power supply. th is instruction can be used s power sleep mode. when pd = "low", power down mode becomes disabled.
s6a0073 34com/60seg driver & controller for dot matrix lcd 30 4) entry mode set (1) re = 0 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 1 i/d s set the moving direction of cursor and display. i/d : incremen t/decrement of ddram address (cursor or blink) when i/d = "high", cursor/blink moves to right and ddram address is increased by 1. when i/d = "low", cursor/blink moves to left and ddram address is decreased by 1. * cgram/segram operates the same as ddram , when read from or write to cgram/segram. when s = "high", after ddram write, the display of enabled line by ds1 - ds4 bits in the shift enable instruction is shifted to the right (i/d = "0") or to the left(i/d = "1"). but it will seem as if the cursor d oes not move. when s = "low", or ddram read, or cgram/segram read/write operation, shift of display as the above function is not performed. (2) re = 1 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 1 1 bid set the data shift direction of segment in the application set. bid : data shift direction of segment when bid = "low", segment data shift direction is set to normal order from seg1 to seg100. when bid = "high", segment data shift direction is set to reversely from seg100 to seg1. by using thi s instruction, the efficiency of application board area can be raised. * the bid setting instruction is recommended to be set at the same time level of function set instruction. * db1 bit must be set to "1".
34com/60seg driver & controller for dot matrix lcd s6a0073 31 5) display on/off control ( re = 0 ) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 1 d c b control display/cursor/blink on/off 1 bit register. d : display on/off control bit when d = "high", entire display is turned on. when d = "low", display is turned off, but display data is rema ined in ddram. c : cursor on/off control bit when c = "high", cursor is turned on. when c = "low", cursor is disappeared in current display, but i/d register remains its data. b : cursor blink on/off control bit when b = "high", cursor blink is on, that pe rforms alternate between all the high data and display character at the cursor position. if fosc has frequency of 270khz, blinking has 370 ms interval. when b = "low", blink is off. 6) extended function set ( re = 1 ) rs r/w db7 db6 db5 db4 db3 db2 db1 d b0 0 0 0 0 0 0 1 f/w b/w nw fw : font width control when fw = "high", display character font width is assigned to 6 - dot and execution time becomes 6/5 times than that of 5 - dot font width. the user font, specified in cgram, is displayed into 6 - dot font wi dth, bit - 5 to bit - 0,including the left most space bit of cgram.(refer to figure 15) when fw = "low", 5 - dot font width is set. b/w : black/white inversion enable bit when b/w = "high", black/white inversion at the cursor position is set. in this case c/b bit of display on/off control instruction becomes don't care condition. if fosc has frequency of 270khz, inversion has 370 ms intervals. nw : 4 line mode enable bit when nw = "high", 4 line display mode is set. in this case n bit of function set instruct ion becomes don't care condition. s p a c e cgrom characte font (5-dot) 8-bit 6-bit cgrom cgram characte font (6-dot) 8-bit 6-bit cgram figure 15. 6 - dot font width cgrom/cgram
s6a0073 34com/60seg driver & controller for dot matrix lcd 32 7) cursor or display shift (re = 0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 s/c r/l - - shift right/left cursor position or display without wr iting or reading of display data. this instruction is used to correct or search display data (refer to table 7). during 2 - line mode display, cursor moves to the 2nd line after 40th digit of 1st line. in 4 - line mode, cursor moves to the next line, only afte r every 20th digit of the current line. note that display shift is performed simultaneously in all the line enabled by ds1 - ds4 in the shift enable instruction. when displayed data is shifted repeatedly, each line shifted individually. when display shift is performed, the contents of address counter are not changed. during low power consumption mode, display shift may not be performed normally. table 7. shift patterns according to s/c and r/l bits s/c r/l operation 0 0 shift cursor to the left, address counter is decreased by 1 0 1 shift cursor to the right, address counter is increased by 1 1 0 shift all the display to the left, cursor moves according to the display 1 1 shift all the display to the right, cursor moves according to the display 8) sh ift/scroll enable (re = 1) (1) dh = 0 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 hs4 hs3 hs2 hs1 hs : horizontal scroll per line enable. this instruction makes valid dot shift by a display line unit. hs1, hs2, hs3 and hs4 indicate each line to b e dot scrolled, and each scroll is performed individually in each line. if you want to scroll the line in 1 - line display mode or the 1st line in 2 - line display mode, set hs1 and hs2 to "high". if the 2nd line scroll is needed in 2 - line mode, set hs3 and hs4 to "high". (refer to table 8) (2) dh = 1 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 ds4 ds3 ds2 ds1 ds : display shift per line enable. this instruction selects shifting line to be shifted according to each line mode in display shift right/l eft instruction. ds1, ds2, ds3 and ds4 indicate each line to be shifted, and each shift is performed individually in each line. if you set ds1 and ds2 to "high" (enable) in 2 line mode, only the 1st line is shifted and the 2nd line is not shifted. when o nly ds1 = "high", only the half of the 1st line is shifted. if all the ds bits (ds1 to ds4) are set to "low" (disable), no display is shifted.
34com/60seg driver & controller for dot matrix lcd s6a0073 33 table 8. relationship between ds and com signal enable bit enabled common signal during shift description hs1/d s1 com1 - com8 hs2/ds2 com9 - com16 hs3/ds3 com17 - com24 hs4/ds4 com25 - com32 the part of display line that corresponds to enabled common signal can be shifted.
s6a0073 34com/60seg driver & controller for dot matrix lcd 34 9) function set (1) re = 0 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 dl n r e(0) dh rev dl : interface data length control bit when dl = "high", it means 8 - bit bus mode with mpu. when dl = "low", it means 4 - bit bus mode with mpu. so to speak, dl is a signal to select 8 - bit or 4 - bit bus mode. in 4 - bit bus mode, it needs to transf er 4 - bit data by two times. n : display line number control bit it is variable only when nw bit of extended function set instruction is low. when n = "low", 1 - line display mode is set. when n = "high", 2 - line display mode is set. when nw = "high", n bi t is invalid, it means 4 - line mode independent of n bit. re : extended function registers enable bit at this instruction, re must be "low". dh : display shift enable selection bit. when dh = "high", enables display shift per line. when dh = "low", enabl es smooth dot scroll. this bit can be accessed only when ie pin input is "high". rev : reverse enable bit when rev = "high", all the display data are reversed. i.e., all the white dots become black and black dots become white. when rev = "low", the di splay mode set normal display.
34com/60seg driver & controller for dot matrix lcd s6a0073 35 (2) re = 1 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 dl n re(0) dh rev dl : interface data length control bit when dl = "high", it means 8 - bit bus mode with mpu. when dl = "low", it means 4 - bit bus mode with mpu . hence, dl is a signal to select 8 - bit or 4 - bit bus mode. when 4 - bit bus mode, it is required to transfer 4 - bit data by two times. n : display line number control bit it is variable only when nw bit of extended function set instruction is low. when n = "low", 1 - line display mode is set. when n = "high", 2 - line display mode is set. when nw = "high", n bit is invalid, it means 4 - line mode independent of n bit. re : extended function registers enable bit when re = "high", extended function set registers, segram address set registers, bid bit, hs/ds bits of shift/scroll enable instruction and be bits of function set register can be accessed. be : cgram/segram data blink enable bit be = "high", makes user font of cgram and segment of segram blinking. the q uantity of blink is assigned the highest 2 bit of cgram/segram. lp : low power consumption mode enable bit when ext input is "low"(without extension driver) and lp bit is set to "high", s6a0073 operates in low power consumption mode. during 1 - line mode s 6a0073 operates on a 4 - division clock, and in 2 - line or 4 - line mode it operates on a 2 - division clock. according to this instruction, execution time becomes 4 or 2 times longer. note not to use display shift instruction, as it may result incorrect operati on. and the frame frequency is lower to 5/6 times lower than that of normal operation.
s6a0073 34com/60seg driver & controller for dot matrix lcd 36 10) set cgram address (re = 0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 ac5 ac4 ac3 ac2 ac1 ac0 set cgram address to ac. this instruction makes cgram data av ailable from mpu. 11) set segram address (re = 1) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 x x ac3 ac2 ac1 ac0 set segram address to ac. this instruction makes segram data available from mpu. 12) set ddram address (re = 0) rs r/w db7 db6 db5 db4 d b3 db2 db1 db0 0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 set ddram address to ac. this instruction makes ddram data available from mpu. in 1 - line display mode (n = 0, nw = 0), ddram address is from "00h" to "4fh". in 2 - line display mode (n = 1, nw = 0), ddra m address in the 1st line is from "00h" to "27h", and ddram address in the 2nd line is from "40h" to "67h". in 4 - line display mode (nw = 1), ddram address is from "00h" to "13h" in the 1st line, from "20h" to "33h" in the 2nd line, from "40h" to "53h" in the 3rd line and from "60h" to "73h" in the 4th line. 13) set scroll quantity (re = 1) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 x sq5 sq4 sq3 sq2 sq1 sq0 as set sq5 to sq0, horizontal scroll quantity can be controlled in dot units. (refer to table 9 ). in this case s6a0073 can show hidden areas of ddram by executing smooth scroll from 1 to 48 dots. table 9. scroll quantity according to hds bits sq5 sq4 sq3 sq2 sq1 sq0 function 0 0 0 0 0 0 no shift 0 0 0 0 0 1 shift left by 1 - dot 0 0 0 0 1 0 shift left by 2 - dot 0 0 0 0 1 1 shift left by 3 - dot : : : : : : : 1 0 1 1 1 1 shift left by 47 - dot 1 1 x x x x shift left by 48 - dot
34com/60seg driver & controller for dot matrix lcd s6a0073 37 14) read busy flag & address rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 this instruction s hows whether s6a0073 is in internal operation or not. if the resultant bf is high, the internal operation is in progress and should wait until bf to be low, which by then the next instruction can be performed. in this instruction the value of address can a lso be read. 15) write data to ram rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write binary 8 - bit data to ddram/cgram/segram. the selection of ram from ddram, cgram, or segram, is set by the previous address set instruction : ddra m address set, cgram address set, segram address set. ram set instruction can also determines the ac direction to ram. after write operation, the address is automatically increased/decreased by 1, according to the entry mode. 16) read data from ram rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read binary 8 - bit data from ddram/cgram/segram. the selection of ram is set by the previous address set instruction. if address set instruction of ram is not performed before this instruction , the data that read first is invalid, as the direction of ac is not determined. if ram data read several times without ram address set instruction before read operation, the correct ram data can be obtained from the second, but the first data would be in correct, as there is no time margin to transfer ram data. in case of ddram read operation, cursor shift instruction plays the same role as ddram address set instruction : it also transfer ram data to output data register. after read operation address coun ter is automatically increased/decreased by 1 according to the entry mode. after cgram/segram read operation, display shift may not be executed correctly. * in case of ram write operation, ac is increased/decreased by 1 like read operation after this. in this time, ac indicates the next address position, but the previous data can only be read by instruction.
s6a0073 34com/60seg driver & controller for dot matrix lcd 38 (2) instruction des cription 2 (ie = "lo w") table 10. instruction set 2 instruction re instruction code description execution time rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 (fosc=270khz) clear display x 0 0 0 0 0 0 0 0 0 1 write "20h" to ddram. and set dram address to "00h" from ac. 1.53ms return home x 0 0 0 0 0 0 0 0 1 x set ddram address to "00h" from ac and return cursor to its or iginal position if shifted. the contents of ddram are not changed. 1.53ms entry mode set x 0 0 0 0 0 0 0 1 i/d s assign cursor moving direction. i/d = "1" : increment, i/d = "0" : decrement. and display shift enable bit. s = "1" :make entire display s hift of all lines during ddram write, s = "0":display shift disable 39 m s display on/off control 0 0 0 0 0 0 0 1 d c b set display/cursor/blink on/off d = "1" : display on, d = "0" : display off, c = "1" : curso r on, c = "0" : cursor off, b = "1" : blink on, b = "0" : blink off. 39 m s extended function set 1 0 0 0 0 0 0 1 fw bw nw assign font width, black/white inverting of cursor, and 4 - line display mode control bit. fw = " 1" : 6 - dot font width, fw = "0" : 5 - dot font width, b/w = "1" : black/white inverting of cursor enable, b/w = "0" : black/white inverting of cursor disable nw = "1" : 4 - line display mode, nw = "0" : 1 - line or 2 - line display m ode 39 m s cursor or display shift 0 0 0 00 0 0 1 s/c r/l x x cursor or display shift. s/c = ? 1 ? : display shift, s/c = ? 0 ? : cursor shift, r/l = ? 1 ? : shift to right, r/l = ? 0 ? : shift to left 39 m s
34com/60seg driver & controller for dot matrix lcd s6a0073 39 table 10. instruction set 2 (continued) instruction re instruction code description execution time rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 (fosc=270khz) scroll enable 1 1 hs4 hs3 hs2 hs1 determine the line for horizontal smooth scro ll. hs1 = "1/0" : 1st line dot scroll enable/disable hs2 = "1/0" : 2nd line dot scroll enable/disable hs3 = "1/0" : 3rd line dot scroll enable/disable hs4 = "1/0" : 4th line dot scroll enable/disable 39 m s function set 0 1 dl n re (0) x x set interface data length dl = "1" : 8 - bit, dl = "0" : 4 - bit numbers of display line when nw = "0", n = "1" : 2 - line, n = "0" : 1 - line extension register, re("0"), 39 m s 1 1 dl n re ( 1) be lp set dl, n, re("1") and cgram/segram blink enable (be) be = " 1/0" : cgram/segram blink enable/disable lp = "1" : low power mode lp = "0" : normal operation mode 39 m s set cgram address 0 0 0 0 1 ac5 ac4 ac3 ac2 ac 1 ac0 set cgram address in address counter. 39 m s set segram address 1 0 0 0 1 x x ac3 ac2 ac1 ac0 set segram address in address counter. 39 m s
s6a0073 34com/60seg driver & controller for dot matrix lcd 40 table 10. instruction set 2 (continued) instruction re instruction code description execution time rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 (fosc=270khz) set ddram address 0 0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 set ddram address in address counter. 39 m s set scroll quantinty 1 1 x sq 5 sq 4 sq 3 sq 2 sq 1 sq 1 set the quantity of horizontal dot scroll. 39 m s read busy flag and address x 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 can be known w hether during internal operation or not by reading bf. the contents of address counter can also be read. bf = " 1 " : busy state, bf = " 0 " : ready state. 0 m s write data x 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write data into internal ram (ddram / cgram / segram). 43 m s read data x 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read data from internal ram (ddram / cgram / segram). 43 m s note: when an mpu program with busy flag (db7) checking is made, 1/2 f osc (is necessary) for executing the next instruction by the falling edge of the 'e' signal after the busy flag (db7) goes to "low".
34com/60seg driver & controller for dot matrix lcd s6a0073 41 1) display clear rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 1 clear all the display data by writing "20h" (space code) to all ddram address, and set ddram address to "00h" into ac (address counter). return cursor to the original status, namely, bring the cursor to the left edge on first line of the display. and entry mode is set to increm ent mode (i/d = "1"). 2) return home rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 1 x return home is cursor return home instruction. set ddram address to "00h" into the address counter. return cursor to its original site and return display to its original status, if shifted. contents of ddram does not change. 3) entry mode set rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 1 i/d s set the moving direction of cursor and display. i/d : increment / decrement of ddram address (cursor or blink) when i/d = "high", cursor/blink moves to right and ddram address is increased by 1. when i/d = "low", cursor/blink moves to left and ddram address is decreased by 1. * cgram/segram operates the same as ddram, when read from or write to cgram/seg ram. when s = "high", after ddram write, the entire display of all lines is shifted to the right (i/d = "low") or to the left(i/d = "high"). but it will seem as if the cursor is not moving. when s = "low", or ddram read, or cgram/segram read/write operat ion, shift of entire display is not performed.
s6a0073 34com/60seg driver & controller for dot matrix lcd 42 4) display on/off control ( re = 0 ) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 1 d c b control display/cursor/blink on/off 1 bit register. d : display on/off control bit when d = "high" , entire display is turned on. when d = "low", display is turned off, but display data is remained in ddram. c : cursor on/off control bit when c = "high", cursor is turned on. when c = "low", cursor is disappeared in current display, but i/d register p reserves its data. b : cursor blink on/off control bit when b = "high", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. if fosc has 270khz frequency, blinking has 370ms interval. when b = "low", blink is off. 5) extended function set ( re = 1 ) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 1 fw bw nw fw : font width control when fw = "high", display character font width is assigned to 6 - dot and execution time becomes 6/5 times t han that of 5 - dot font width. the user font, specified in cgram, is displayed into 6 - dot font width, bit - 5 to bit - 0,including the leftmost space bit of cgram.(refer to figure 16). when fw = "low", 5 - dot font width is set. b/w : black/white inversion enable bit when b/w = "high", black/white inversion at the cursor position is set. in this case c/b bit of display on/off control instruction becomes don't care condition. if fosc has frequency of 270khz, inversion has 370ms intervals. nw : 4 line mode enable bit when nw = "high", 4 line display mode is set. in this case n bit of function set instruction becomes don't care condition.
34com/60seg driver & controller for dot matrix lcd s6a0073 43 s p a c e cgrom characte font (5-dot) 8-bit 6-bit cgrom cgram characte font (6-dot) 8-bit 6-bit cgram figure 16. 6 - dot font width cgrom/cgram 6) cursor or display shift (re = 0) rs r/w db7 db6 d b5 db4 db3 db2 db1 db0 0 0 0 0 0 1 sc r/l - - shift right/left cursor position or display without writing or reading of display data. this instruction is used to correct or search display data (refer to table 7). during 2 - line mode display, cursor moves to the 2nd line after 40th digit of 1st line. in 4 - line mode, cursor moves to the next line, only after every 20th digit of the current line. note that display shift is performed simultaneously in all the line. when displayed data is shifted repeatedly, e ach line shifted individually. when display shift is performed, the contents of address counter are not changed. table 11. shift patterns according to s/c and r/l bits s/c r/l operation 0 0 shift cursor to the left, address counter is decreased by 1 0 1 shift cursor to the right, address counter is increased by 1 1 0 shift all the display to the left, cursor moves according to the display 1 1 shift all the display to the right, cursor moves according to the display
s6a0073 34com/60seg driver & controller for dot matrix lcd 44 7) scroll enable (re = 1) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 hs4 hs3 hs2 hs1 hs : horizontal scroll per line enable this instruction makes valid dot shift by a display line unit. hs1, hs2, hs3 and hs4 indicate each line to be dot scrolled, and each scroll is p erformed individually in each line. if the line in 1 - line display mode or the 1st line in 2 - line display mode is to be scrolled, set hs1 and hs2 to "high". if the 2nd line scroll is needed in 2 - line mode, set hs3 and hs4 to "high". (refer to table 8) 8) function set (1) re = 0 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 dl n re(0) - - dl : interface data length control bit when dl = "high", it means 8 - bit bus mode with mpu. when dl = "low", it means 4 - bit bus mode with mpu. hence, dl is a signal to select 8 - bit or 4 - bit bus mode. when 4 - bit bus mode, it is required to transfer 4 - bit data twice. n : display line number control bit it is variable only when nw bit of extended function set instruction is low. when n = "low", 1 - line display mode is set. when n = "high", 2 - line display mode is set. when nw = "high", n bit is invalid, it means 4 - line mode independent of n bit. re : extended function registers enable bit at this instruction, re must be "low".
34com/60seg driver & controller for dot matrix lcd s6a0073 45 (2) re = 1 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 dl n re(1) re lp dl : interface data length control bit when dl = "high", it means 8 - bit bus mode with mpu. when dl = "low", it means 4 - bit bus mode with mpu. so to speak, dl is a signal to select 8 - bit or 4 - bit bus mode. when 4 - bit bus mode, it is required to transfer 4 - bit data twice. n : display line number control bit it is variable only when nw bit of extended function set instruction is low. when n = "low", 1 - line display mode is set. when n = "high", 2 - line disp lay mode is set. when nw = "high", n bit is invalid, it means 4 - line mode independent of n bit. re : extended function registers enable bit when re = "high", extended function set registers, segram address set registers, hs bits of scroll enable instruct ion and be bits of function set register can be accessed. be : cgram/segram data blink enable bit be = "high", makes user font of cgram and segment of segram blinking. the quantity of blink is assigned the highest 2 bit of cgram/segram. lp : low power co nsumption mode enable bit when ext port input is "low"(without extension driver) and lp bit is set to "high", s6a0073 operates in low power consumption mode. during 1 - line mode s6a0073 operates on a 4 - division clock, and in 2 - line or 4 - line mode it oper ates on a 2 - division clock. according to this instruction, execution time becomes 4 or 2 times longer. note not to use display shift instruction, it may happen wrong operation. and the frame frequency is lower to 5/6 than that of normal operation. 9) se t cgram address (re = 0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 ac5 ac4 ac3 ac2 ac1 ac0 set cgram address to ac. this instruction makes cgram data available from mpu.
s6a0073 34com/60seg driver & controller for dot matrix lcd 46 10) set segram address (re = 1) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 x x ac3 ac2 ac1 ac0 set segram address to ac. this instruction makes segram data available from mpu. 11) set ddram address (re = 0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 set ddram address to ac. this instr uction makes ddram data available from mpu. in 1 - line display mode (n = 0, nw = 0), ddram address is from "00h" to "4fh". in 2 - line display mode (n = 1, nw = 0), ddram address in the 1st line is from "00h" to "27h", and ddram address in the 2nd line is f rom "40h" to "67h". in 4 - line display mode (nw = 1), ddram address is from "00h" to "13h" in the 1st line, from "20h" to "33h" in the 2nd line, from "40h" to "53h" in the 3rd line and from "60h" to "73h" in the 4th line. 12) set scroll quantity (re = 1) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 x sq5 sq4 sq3 sq2 sq1 sq0 setting sq5 to sq0, horizontal scroll quantity can be controlled in dot units. (refer to table 12). in this case s6a0073 execute dot smooth scroll from 1 to 48 dots. table 12. scroll quantity according to hds bits sq5 sq4 sq3 sq2 sq1 sq0 function 0 0 0 0 0 0 no shift 0 0 0 0 0 1 shift left by 1 - dot 0 0 0 0 1 0 shift left by 2 - dot 0 0 0 0 1 1 shift left by 3 - dot : : : : : : : 1 0 1 1 1 1 shift left by 47 - dot 1 1 x x x x shift l eft by 48 - dot
34com/60seg driver & controller for dot matrix lcd s6a0073 47 13) read busy flag & address rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 this instruction shows whether s6a0073 is in internal operation or not. if the resultant bf is high, the internal operation is in progress and should wait until bf becomes "low", which by then the next instruction can be performed. in this instruction value of address counter can also be read. 14) write data to ram rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write binary 8 - bit data to ddram/cgram/segram. the selection of ram from ddram, cgram, or segram, is set by the previous address set instruction : ddram address set, cgram address set, segram address set. ram set instruction can also determines the ac di rection to ram. after write operation, the address is automatically increased/decreased by 1, according to the entry mode. 15) read data from ram rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read binary 8 - bit data from ddram/cgram /segram. the selection of ram is set by the previous address set instruction. if address set instruction of ram is not performed before this instruction, the data that read first is invalid, because the direction of ac is not determined. if the ram data s everal is read times without ram address set instruction before read operation, the correct ram data from the second, but the first data would be incorrect, as there is no time margin to transfer ram data. in case of ddram read operation, cursor shift inst ruction plays the same role as ddram address set instruction : it also transfer ram data to output data register. after read operation address counter is automatically increased/decreased by 1 according to the entry mode. after cgram/segram read operatio n, display shift may not be executed correctly. * in case of ram write operation, after this ac is increased/decreased by 1 as in read operation after this. in this time, ac indicates the next address position, but the previous data can only be read by rea d instruction.
s6a0073 34com/60seg driver & controller for dot matrix lcd 48 interface with mpu s6a0073 can transfer data in bus mode (4 - bit or 8 - bit) or serial mode with mpu. hence, both types 4 or 8 - bit mpu can be used. in case of 4 - bit bus mode, data transfer is performed by two times to transfer 1 byte da ta. (1) when interfacing data length are 4 - bit, only 4 ports, from db4 to db7, are used as data bus. at first higher 4 - bit (in case of 8 - bit bus mode, the contents of db4 - db7) are transferred, and then lower 4 - bit (in case of 8 - bit bus mode, the conten ts of db0 - db3) are transferred. so transfer is performed by two times. busy flag outputs "high" after the second transfer are ended. (2) when interfacing data length are 8 - bit, transfer is performed at a time through 8 ports, from db0 to db7. (3) if im is set to "low", serial transfer mode is set.
34com/60seg driver & controller for dot matrix lcd s6a0073 49 interface with mpu i n bus mode 1) interface with 8 - bits mpu if 8 - bits mpu is used, s6a0073 can connect directly with that. in this case, port e, rs, r/w and db0 to db7 need to interface ea ch other. example of timing sequence is shown below. rs r/w e internal signal db7 internal operation data busy busy no busy data instruction busy flag check instruction busy flag check busy flag check figure 17. example of 8 - bit bus mode timing sequence 2) interface with 4 - bits mpu if 4 - bits mpu is used, s6a0073 can connect directly with this. in this case, e, rs, r/w and db4 to db7 need to interface each other. the transfer is performed by twice. example of timing sequence is shown below. rs r/w e internal signal db7 internal operation d7 busy ac3 no busy instruction busy flag check instruction busy flag check d3 ac3 d7 d3 fig 18. example of 4 - bit bus mode timing sequence
s6a0073 34com/60seg driver & controller for dot matrix lcd 50 interface with mpu in serial mode when im input is "low", seri al interface mode is started. at this time, all three ports, sclk (synchronizing transfer clock), sid (serial input data), and sod (serial output data), are used. if s6a0073 is to be used with other chips, chip select port (cs) can be used. by setting cs t o "low", s6a0073 can receive sclk input. if cs is set to "high", s6a0073 reset the internal transfer counter. before transfer real data, start byte has to be transferred. it is composed of succeeding 5 "high" bits, register read write control bit (r/w), register selection bit (rs) and end bit that indicates the end of start byte. whenever succeeding 5 "high" bits are detected by s6a0073, it resets the serial transfer counter and prepares to receive next information. the next input data is the register sel ection bit which determines which register will be used, and read write control bit that determine the direction of data. then end bit is transferred, which must have "low" value to show the end of start byte. (refer to figure 19, figure 20) (1) write oper ation (r/w = 0) after start byte is transferred from mpu to s6a0073, 8 - bit data is transferred which is divided into 2 bytes, each byte has 4 bit's real data and 4 bit's partition token data. for example, if real data is "10110001" (d0 - d7), then serially transferred data becomes "1011 0000 0001 0000" where 2nd and 4th 4 bits must be "0000" for safe transfer. to transfer several bytes continuously without changing rs bit and rw bit, start byte transfer is needed only at first starting time, i, e, after fir st start byte is transferred, real data succeeding can be transferred. (2) read operation (r/w = 1) after start byte is transferred to s6a0073, mpu can receive 8 - bit data through the sod at a time from the lsb. waiting time is needed to insert between sta rt byte and data reading, as internal reading from ram requires some delay. continuous data reading is possible such as serial write operation. it also needs only one start bytes, only if some delay between reading operations of each byte is inserted. duri ng the reading operation, s6a0073 observes succeeding 5 "high" from mpu. if it is detected, s6a0073 restarts serial operation at once and prepares to receive rs bit. so in continuous reading operation, sid port must be "low".
34com/60seg driver & controller for dot matrix lcd s6a0073 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 r/w rs 0 d0 d1 d2 d3 0 0 0 0 d4 d5 d6 d7 0 0 0 0 1 1 1 1 1 starting byte synchronizing bit string instruction lower data upper data 1'st byte 2'nd byte cs (input) sclk (input) sid (input) serial write operation 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 rs d0 d1 d2 d3 0 0 0 0 1 1 1 1 1 starting byte synchronizing bit string busy flag/ read data lower data cs (input) sclk (input) sid (input) serial read operation r/w 0 0 0 0 0 d4 d5 d6 d7 upper data sod (output) figure 19. timing diagram of serial data transfer
s6a0073 34com/60seg driver & controller for dot matrix lcd 52 start byte 1'st byte 2'nd byte 1'st byte 2'nd byte instruction1 instruction2 instruction3 instruction1 execution time instruction2 execution time instruction3 execution time sclk sid continuous write operation instruction1 execution time instruction2 execution time instruction3 execution time sclk sid continuous read operation start byte data read3 data read2 data read1 wait wait wait wait wait sod 1'st byte 2'nd byte fig 20. timing diagram of continuous data transfer
34com/60seg driver & controller for dot matrix lcd s6a0073 53 application informat ion according to lcd panel 1) lcd panel: 24 character x 1 - line format (5 - dot font,1/17 duty) s6a0073 com1 com2 com3 com4 com5 com6 com7 com8 com17 (com0) seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg58 seg59 seg60 com16 com15 com14 com13 com12 com11 com10 com9 2) lcd panel: 24 character x 2 - line format (5 - dot font, 1/33 duty) s6a0073 com1 com2 com3 com4 com5 com6 com7 com8 com17 com18 com19 com20 com21 com22 com23 com24 seg1 seg2 seg3 seg58 seg59 seg60 com32 com31 com30 com29 com28 com33 (com0) seg4 seg5 com27 com26 com25 com16 com15 com14 com13 com12 com11 com10 com9
s6a0073 34com/60seg driver & controller for dot matrix lcd 54 3) lcd panel: 12 character x 4 - line format (5 - dot font, 1/33 duty) s6a0073 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 seg1 seg2 seg3 seg26 seg27 seg28 com32 com31 com30 com29 com28 com33 (com0) seg4 seg5 com27 com26 com25 com17 com18 com19 com20 com21 com22 com23 com24 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg58 seg59 seg60 %
34com/60seg driver & controller for dot matrix lcd s6a0073 55 4) lcd panel: 10 charact er 4 - line format (6 - dot font, 1/33 duty) s6a0073 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 seg1 seg2 seg3 seg31 seg32 seg33 com32 com31 com30 com29 com28 com33 (com0) seg4 seg5 com27 com26 com25 com17 com18 com19 com20 com21 com22 com23 com24 seg6 seg34 seg35 seg36 seg58 seg59 seg60
s6a0073 34com/60seg driver & controller for dot matrix lcd 56 5) lcd panel: 20 character 4 - line format (5 - dot font, 1/33 duty) s6a0073 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 seg1 seg2 seg3 seg58 seg59 seg60 com32 com31 com30 com29 com28 com33 (com0) seg4 seg5 com27 com26 com25 com17 com18 com19 com20 com21 com22 com23 com24 seg1 seg2 seg3 seg4 seg5 seg36 seg37 seg38 seg39 seg40 extension driver ext vdd
34com/60seg driver & controller for dot matrix lcd s6a0073 57 initializ ing 1) initializing by internal reset circuit when the power is turned on, s6a0073 is initialized automatically by power on reset circuit. during the initialization, the following instructions are executed, and bf(busy flag) is kept "high"(busy state) to the end of initialization. (1) display clear instruction write "20h" to all ddram (2) set functions instruction dl = 1 : 8 - bit bus mode n = 1 : 2 - line display mode re = 0 : extension register disable be = 0 : cgram/segram blink off lp = 0 : operate in normal mode (not in low power mode) dh = 0 : horizontal scroll enable rev = 0 : normal display mode (not reversed display) (3)control display on/off instruction d = 0 : display off c = 0 : cursor off b = 0 : blink off (4) set entry mode instruction i/d = 1 : increment by 1 s = 0 : no entire display shift bid = 0 : normal direction segment port (5) set extension function instruction fw = 0 : 5 - dot font width character display b/w = 0 : normal cursor (8th line) nw = 0 : not 4 - line display mode, 2 - line mode is set because of n("1") (6) enable scroll/shift instruction hs = 0000 : scroll per line disable ds = 0000 : shift per line disable (7) set scroll quantity instruction sq = 000000 : not scroll 2) initializing by hardware reset input when reset pin = "low", s6a0073 can be initialized like the case of power on reset. during the power on reset operation, this pin is ignored.
s6a0073 34com/60seg driver & controller for dot matrix lcd 58 initializing by inst ruction 1) 8 - bit interface mode power on wait for more than 20ms after v dd rises to 4.5v wait for more than 30ms after v dd rises to 2.7v rs r/w db7 db6 db5 db4 db3 db2 db1 db0 function set 0 0 0 0 1 dl(1) n 0 x x wait for more than 39 m s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 display on/off control 0 0 0 0 0 0 1 d c b wait for more than 39 m s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 display clear 0 0 0 0 0 0 0 0 0 1 wait for more than 1.53 ms rs r/w db7 db6 db5 db4 db3 db2 db1 db0 entry mode set 0 0 0 0 0 0 0 1 i/d s initialization end dl 0 1 1-line mode 2-line mode n 0 1 4-bit interface 8-bit interface d 0 1 display off display on c 0 1 cursor off cursor on b 0 1 blink off blink on i/d 0 1 decrement mode increment mode s 0 1 entire shift off entire shift on condition: fosc = 270khz
34com/60seg driver & controller for dot matrix lcd s6a0073 59 2) 4 - bit interface mode power on wait for more than 20ms after v dd rises to 4.5v wait for more than 30ms after v dd rises to 2.7v rs r/w db7 db6 db5 db4 db3 db2 db1 db0 function set 0 0 0 0 1 dl(0) x x x x wait for more than 39 m s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 display on/off control wait for more than 39 m s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 clear display wait for more than 1.53 ms rs r/w db7 db6 db5 db4 db3 db2 db1 db0 entry mode set initialization end dl 0 1 1-line mode 2-line mode n 0 1 4-bit interface d 0 1 display off display on c 0 1 cursor off cursor on b 0 1 blink off blink on i/d 0 1 decrement mode increment mode sh 0 1 entire shift off entire shift on 0 0 0 0 0 0 x x x x 0 0 1 d c b x x x x 0 0 0 0 0 0 x x x x 0 0 0 1 i/d sh x x x x 0 0 0 0 0 0 x x x x 0 0 0 0 0 1 x x x x condition: fosc = 270khz rs r/w db7 db6 db5 db4 db3 db2 db1 db0 function set 0 0 0 0 1 0 x x x x 0 0 n 0 x x x x x x wait for more than 39 m s 8-bit interface
s6a0073 34com/60seg driver & controller for dot matrix lcd 60 example of instructi on and display corre spondence 1) ie = "low" 1. power supply on: initialized by the internal power on reset circuit rs r/w db7 db6 db5 db4 db3 db2 db1 db0 lcd display 2. function set: 8-bit, 1-line, re (0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 1 0 0 x x 3. display on/off control: display/cursor on rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 1 1 1 0 _ 4. entry mode set: increment rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 1 1 0 s _ 5. write data to ddram: write s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 0 1 0 0 1 1 _ 6. write data to ddram: write a rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 0 0 0 0 0 1 sa _ 7. write data to ddram: write m rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 0 0 1 1 0 1 sam _ 8. write data to ddram: write s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 0 1 0 0 1 1 sams _
34com/60seg driver & controller for dot matrix lcd s6a0073 61 9. write data to ddram: write u rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 lcd display samsu_ 0 0 1 0 1 0 1 0 1 10. write data to ddram: write n rs r/w db7 db6 db5 db4 db3 db2 db1 db0 11. write data to ddram: write g rs r/w db7 db6 db5 db4 db3 db2 db1 db0 12. cursor or display shift: cursor shift to right rs r/w db7 db6 db5 db4 db3 db2 db1 db0 13. entry mode set: entire display shift enable rs r/w db7 db6 db5 db4 db3 db2 db1 db0 14. write data to ddram: write k rs r/w db7 db6 db5 db4 db3 db2 db1 db0 15. write data to ddram: write s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 16. write data to ddram: write 0 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 1 x x 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 1 0 1 1 1 0 0 1 0 1 0 0 1 1 1 0 0 0 1 1 0 0 0 0 samsun_ samsung_ samsung _ amsung k_ msung ks_ sung ks0_ samsung _
s6a0073 34com/60seg driver & controller for dot matrix lcd 62 17. write data to ddram: write 0 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 lcd display ung ks00_ 0 0 0 1 1 0 0 0 0 18. write data to ddram: write 7 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 19. write data to ddram: write 2 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 20. cursor or display shift: cursor shift left rs r/w db7 db6 db5 db4 db3 db2 db1 db0 21. write data to ddram: write 8 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 22. return home rs r/w db7 db6 db5 db4 db3 db2 db1 db0 23. clear display rs r/w db7 db6 db5 db4 db3 db2 db1 db0 ng ks007_ g KS0073 _ KS0073_ s amsung KS0073 _ 1 0 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 x x 1 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1 x 0 0 0 0 0 0 0 0 0 1 g ks007 3
34com/60seg driver & controller for dot matrix lcd s6a0073 63 2) ie = "high" 1. power supply on: initialized by the internal power on reset circuit rs r/w db7 db6 db5 db4 db3 db2 db1 db0 2. function set: 8-bit, re(1) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 3. extended function set: 5-font, 4-line rs r/w db7 db6 db5 db4 db3 db2 db1 db0 4. function set: re(0) rs r/w db7 db6 db5 db4 db3 db2 db1 db0 5. display on/off control: display/cursor on rs r/w db7 db6 db5 db4 db3 db2 db1 db0 6. write data to ddram: write s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 1 _ s_
s6a0073 34com/60seg driver & controller for dot matrix lcd 64 7. write data to ddram: write a rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 sa_ 0 0 1 0 0 0 0 0 1 12. write data to ddram: write g rs r/w db7 db6 db5 db4 db3 db2 db1 db0 13. set ddram address 20h rs r/w db7 db6 db5 db4 db3 db2 db1 db0 14. write data to ddram: write k rs r/w db7 db6 db5 db4 db3 db2 db1 db0 19. write data to ddram: write 3 rs r/w db7 db6 db5 db4 db3 db2 db1 db0 20. set ddram address 40h rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 0 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 1 1 0 0 0 1 1 0 1 1 1 0 0 1 1 0 0 0 0 0 0 samsung_ samsung _ samsung k_ samsung KS0073_ samsung KS0073 _
34com/60seg driver & controller for dot matrix lcd s6a0073 65 21. write data to ddram: write l rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 samsung KS0073 l_ 0 0 1 0 0 1 1 0 0 30. write data to ddram: write r rs r/w db7 db6 db5 db4 db3 db2 db1 db0 31. set ddram address 60h rs r/w db7 db6 db5 db4 db3 db2 db1 db0 43. write data to ddram: write r rs r/w db7 db6 db5 db4 db3 db2 db1 db0 44. function set: re("0"), dh("1") rs r/w db7 db6 db5 db4 db3 db2 db1 db0 45. function set: re("1") rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 0 1 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 1 0 0 samsung KS0073 lcd driver_ samsung KS0073 lcd driver _ samsung KS0073 lcd driver & controller_ samsung KS0073 lcd driver & controller_ samsung KS0073 lcd driver & controller_
s6a0073 34com/60seg driver & controller for dot matrix lcd 66 46. shift/scroll enable: ds4("1"), ds3/2/1("0") rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 samsung KS0073 lcd driver & controller_ 0 0 0 0 1 1 0 0 0 47. function set: re("0") rs r/w db7 db6 db5 db4 db3 db2 db1 db0 48. cursor or display shift: display shift to left rs r/w db7 db6 db5 db4 db3 db2 db1 db0 49. cursor or display shift: display shift to left rs r/w db7 db6 db5 db4 db3 db2 db1 db0 50. cursor or display shift: display shift to left rs r/w db7 db6 db5 db4 db3 db2 db1 db0 51. cursor or display shift: display shift to left rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 1 1 0 x x 0 0 0 0 0 1 1 0 x x 0 0 0 0 0 1 1 0 x x 0 0 0 0 0 1 1 0 x x samsung KS0073 lcd driver & controller_ samsung KS0073 lcd driver controller_ samsung KS0073 lcd driver controller_ samsung KS0073 lcd driver ontroller_ samsung KS0073 lcd driver ntroller_
34com/60seg driver & controller for dot matrix lcd s6a0073 67 52. return home rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 s amsung KS0073 lcd driver & controller 0 0 0 0 0 0 0 1 x 53. function set: re("0), rev("1") rs r/w db7 db6 db5 db4 db3 db2 db1 db0 54. cursor or display shift: display shift to right rs r/w db7 db6 db5 db4 db3 db2 db1 db0 55. cursor or display shift: display shift to right rs r/w db7 db6 db5 db4 db3 db2 db1 db0 56. return home rs r/w db7 db6 db5 db4 db3 db2 db1 db0 57. function set: re("0"), rev("0") rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 1 1 0 1 1 0 0 0 0 0 1 1 1 x x 0 0 0 0 0 1 1 1 x x 0 0 0 0 0 0 0 0 1 x 0 0 0 0 1 1 1 0 0 0 s amsung KS0073 lcd driver & controller s amsung KS0073 lcd driver & controller s amsung KS0073 lcd driver & controller s amsung KS0073 lcd driver & controller s amsung KS0073 lcd driver & controller
s6a0073 34com/60seg driver & controller for dot matrix lcd 68 58. function set: re("1") rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 s amsung KS0073 lcd driver & controller 0 0 0 1 1 1 1 0 0 59. entry mode set: bid("1") rs r/w db7 db6 db5 db4 db3 db2 db1 db0 60. write data to ddram: write b rs r/w db7 db6 db5 db4 db3 db2 db1 db0 61. write data to ddram: write i rs r/w db7 db6 db5 db4 db3 db2 db1 db0 62. write data to ddram: write d rs r/w db7 db6 db5 db4 db3 db2 db1 db0 63. clear display rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 _
34com/60seg driver & controller for dot matrix lcd s6a0073 69 frame frequency 1) 1/17 duty cycle ... ... 17 16 3 2 1 17 16 4 3 2 1 1-line selection period vdd v1 v4 v5 . . com1 1 frame 1 frame item normal display mode (lp = 0) 5 - dot font width 6 - dot font width 1 - line selection period 200 clocks 240 clocks frame frequency 79.4hz 66.2hz item low power mode (lp = 1) 5 - dot font width 6 - dot font width 1 - line selection period 60 clocks 72 clocks frame frequency 66.2hz 55.1hz * fosc = 270khz (1 clo ck = 3.7 m s)
s6a0073 34com/60seg driver & controller for dot matrix lcd 70 2) 1/33 duty cycle ... ... 33 32 3 2 1 33 32 4 3 2 1 1-line selection period vdd v1 v4 v5 . . com1 1 frame 1 frame item normal display mode (lp = 0) 5 - dot font width 6 - dot font width 1 - line selection period 100 clocks 120 clocks frame frequency 81.8hz 68.2hz item normal display mode (lp = 1) 5 - d ot font width 6 - dot font width 1 - line selection period 60 clocks 72 clocks frame frequency 68.2hz 56.8hz ?? fosc = 270khz (1 clock = 3.7 m s)
34com/60seg driver & controller for dot matrix lcd s6a0073 71 power supply for dri ving lcd panel 1) when an external power supply is used vdd v1 v2 v3 v4 v5 vdd r r r r vee r0 2 ) when an internal booster is used vdd v1 v2 v3 v4 v5 vdd r r r r r0 v ci gnd c1 c2 v5out2 v5out3 can be detached if not using power down mode 1 m f + - 1 m f + - + - boosting twice vdd v1 v2 v3 v4 v5 vdd r r r r r0 v ci gnd c1 c2 v5out2 v5out3 can be detached if not using power down mode 1 m f + - 1 m f + - + - boosting three times 1 m f + - notes: 1. boosted output voltage should not exceed the maximum value (13 v) of the lcd driving voltage. especially, a voltage of over 4.3v should not be input to the reference voltage(vci ) when boosting three times. 2. a voltage of over 5.5v should not be input to the reference voltage (vci) when boosting twice. 3. the value of resistance, according to the number of lines, duty ratio and the bias, is shown below. (refer to table 13)
s6a0073 34com/60seg driver & controller for dot matrix lcd 72 table 13. duty ratio and power supply for lcd driving item data number of lines 1 2 or 4 duty ratio 1/17 1/33 bias 1/5 1/6.7 divided resistance r r r r0 r 2.7r maximum absolute rat e characteristic symbol value unit power supply vo ltage (1) v dd - 0.3 to +7.0 v power supply voltage (2) v lcd v dd - 15.0 to v dd +0.3 v input voltage v in - 0.3 to v dd +0.3 v operating temperature t opr - 30 to +80 c storage temperature t stg - 55 to +125 c ?? voltage greater than above may damage to the circuit (v dd 3 v1 3 v2 3 v3 3 v4 3 v5)
34com/60seg driver & controller for dot matrix lcd s6a0073 73 electrical character istics dc characteristics (v dd = 2.7v to 5.5v, ta = - 30 to +85 c) characteristic symbol condition min typ max unit operating voltage v dd - 2.7 - 5.5 v supply current i dd internal oscillation or external clock. (v dd =3.0v, f osc = 270khz) - 0.15 0.3 ma input voltage (1) v ih1 - 0.7v dd - v dd (except osc1) v il1 v dd = 2.7 to 3.0 - 0.3 - 0.2v dd v v dd = 3.0 to 5.5 - 0.3 - 0.6 input voltage (2) v ih2 - 0.7v dd - v dd v (osc1) v il2 - - - 0.2v dd output voltage (1) v oh1 i oh = - 0.1ma 0.75v dd - - v (db0 to db7) v ol1 i ol = 0.1ma - - 0.2v dd output voltage (2) v oh2 i o = - 40 m a 0.8v dd - - v (expect db0 to db7) v ol2 i o = 40 m a - - 0.2v dd voltage drop vd com i o = 0. 1ma - - 1 v vd seg - - 1 input leakage current i il v in = 0v to v dd - 1 - 1 m a low input current i in v in = 0v, v dd = 3v (pull up) - 10 - 50 - 120 internal clock (external r f ) f osc rf = 91k w 2% (v dd = 5v) 190 270 350 k hz f ec 125 270 410 khz external clock duty - 45 50 55 % t r , t f - - 0.2 m s voltage converter out2 (vci = 4.5v) v out2 ta = 25 c, c = 1 m f, i out = 0.25ma, - 3.0 - 4.2 - v voltage converter out3 (vci = 2.7v) v out3 f osc = 270khz - 4.3 - 5.1 - voltage converter input vci - 2.5 - 4.5 lcd driving voltage v lcd v dd - v5 1/5 bias 3.0 - 13.0 v 1/6.7 bias 3.0 - 13.0
s6a0073 34com/60seg driver & controller for dot matrix lcd 74 ac characteristics (v dd = 4.5 to 5.5v, ta = - 30 to +85 c) mode item symb ol min typ max unit e cycle time t c 500 - - e rise / fall time t r , t f - - 20 (1) write mode e pulse width (high, low) t w 230 - - ( refer to figure 21) r/w and rs setup time t su1 40 - - ns r/w and rs hold time t h1 10 - - data setup time t su2 6 0 - - data hold time t h2 10 - - e cycle time t c 500 - - e rise / fall time t r , t f - - 20 (2) read mode e pulse width (high, low) t w 230 - - (refer to figure 22) r/w and rs setup time t su 40 - - ns r/w and rs hold time t h 10 - - data outpu t delay time t d - - 160 data hold time t dh 5 - - serial clock cycle time t c 0.5 - 20 m s serial clock rise / fall time t r ,t f - - 50 serial clock width (high, low) t w 200 - - (3) serial chip select setup time t su1 60 - - interface mode chip select hold time th1 20 - - ns (refer to figure 23) serial input data setup time t su2 100 - - serial input data hold time t h2 100 - - serial output data delay time t d - - 160 serial output data hold time t dh 5 - -
34com/60seg driver & controller for dot matrix lcd s6a0073 75 ac characteristics (continued) (v dd = 2.7 to 4.5v, ta = - 30 to +85 c) mode item symbo l min typ max unit e cycle time t c 1000 - - e rise / fall time t r , t f - - 25 (4) write mode e pulse width (high, low) t w 450 - - ( refer to figure 21) r/w and rs setup time t su1 60 - - ns r/w and rs hold time t h1 20 - - data setup time t su2 1 95 - - data hold time t h2 10 - - e cycle time t c 1000 - - e rise / fall time t r , t f - - 25 (5) read mode e pulse width (high, low) t w 450 - - (refer to figure 22) r/w and rs setup time t su 60 - - ns r/w and rs hold time t h 20 - - data out put delay time t d - - 360 data hold time t dh 5 - - serial clock cycle time t c 1 - 20 m s serial clock rise / fall time t r ,t f - - 50 serial clock width (high, low) t w 400 - - (6) serial chip select setup time t su1 60 - - interface mode chip select hold time t h1 20 - - ns (refer to figure 23) serial input data setup time t su2 200 - - serial input data hold time t h2 200 - - serial output data delay time t d - - 360 serial output data hold time t dh 5 - -
s6a0073 34com/60seg driver & controller for dot matrix lcd 76 ac characteristics (continued) (v dd = 2.7 to 5.5v, ta = - 30 to + 85 c) mode item symbol m in typ max unit clock pulse width (high, low) t w 800 - - (7) interface mode clock rise / fall time t r , t f - - 100 with extension clock setup time t su1 500 - - ns driver data setup time t su2 300 - - (refer to figure 24) data hold time t dh 300 - - m delay time t dm - 1000 - 1000 v ih1 v il1 t su1 v il1 t h 1 v il1 t h 1 t f t w t h 2 v ih1 v il1 t su2 t r v ih1 v il1 valid data v ih1 v il1 t c db0 - db7 e r/w rs v il1 v ih1 v il1 figure 21. write mode
34com/60seg driver & controller for dot matrix lcd s6a0073 77 v ih1 v il1 t su v ih1 t h v ih1 t h t f t w t dh v ih1 v il1 t r v ih1 v il1 valid data v ih1 v il1 t c db0 - db7 e r/w rs t d v il1 v ih1 v il1 figure 22. read mode v il1 t su1 t h1 sod sid sclk cs v ih1 v il1 t w t w t c t r v ih1 v il1 v ih1 v il1 v ih1 v il1 t dh v oh1 v ol1 t d t su2 t h2 tf v il1 figure 23. serial interface mode
s6a0073 34com/60seg driver & controller for dot matrix lcd 78 m d clk2 clk1 v oh2 t r t w v oh2 v ol2 t f v oh2 v ol2 v oh2 t w v ol2 t w t su1 v oh2 v ol2 t dh t dm v ol2 t su1 figure 24. interface mode with e xtension driver reset timing (v dd = 2.7 to 5.5v, ta = - 30 to +85 c) it e m symbol min typ max unit reset low level width (refer to figure 2 5 ) t res 10 - - ms reset v il1 v il1 t res figure 25. reset timing diagram

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